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177 lines
9.2 KiB
177 lines
9.2 KiB
/********************************** (C) COPYRIGHT ******************************* |
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* File Name : ch32v00x_dma.h |
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* Author : WCH |
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* Version : V1.0.0 |
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* Date : 2022/08/08 |
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* Description : This file contains all the functions prototypes for the |
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* DMA firmware library. |
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********************************************************************************* |
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. |
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* Attention: This software (modified or not) and binary are used for |
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* microcontroller manufactured by Nanjing Qinheng Microelectronics. |
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*******************************************************************************/ |
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#ifndef __CH32V00x_DMA_H |
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#define __CH32V00x_DMA_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#include <ch32v00x.h> |
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/* DMA Init structure definition */ |
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typedef struct |
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{ |
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uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ |
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uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ |
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uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. |
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This parameter can be a value of @ref DMA_data_transfer_direction */ |
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uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. |
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The data unit is equal to the configuration set in DMA_PeripheralDataSize |
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or DMA_MemoryDataSize members depending in the transfer direction. */ |
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uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. |
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This parameter can be a value of @ref DMA_peripheral_incremented_mode */ |
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uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. |
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This parameter can be a value of @ref DMA_memory_incremented_mode */ |
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uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. |
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This parameter can be a value of @ref DMA_peripheral_data_size */ |
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uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. |
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This parameter can be a value of @ref DMA_memory_data_size */ |
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uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. |
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This parameter can be a value of @ref DMA_circular_normal_mode. |
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@note: The circular buffer mode cannot be used if the memory-to-memory |
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data transfer is configured on the selected Channel */ |
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uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. |
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This parameter can be a value of @ref DMA_priority_level */ |
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uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. |
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This parameter can be a value of @ref DMA_memory_to_memory */ |
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} DMA_InitTypeDef; |
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/* DMA_data_transfer_direction */ |
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#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) |
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#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) |
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/* DMA_peripheral_incremented_mode */ |
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#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) |
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#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) |
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/* DMA_memory_incremented_mode */ |
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#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) |
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#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) |
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/* DMA_peripheral_data_size */ |
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#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) |
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#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) |
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#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) |
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/* DMA_memory_data_size */ |
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#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) |
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#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) |
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#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) |
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/* DMA_circular_normal_mode */ |
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#define DMA_Mode_Circular ((uint32_t)0x00000020) |
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#define DMA_Mode_Normal ((uint32_t)0x00000000) |
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/* DMA_priority_level */ |
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#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) |
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#define DMA_Priority_High ((uint32_t)0x00002000) |
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#define DMA_Priority_Medium ((uint32_t)0x00001000) |
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#define DMA_Priority_Low ((uint32_t)0x00000000) |
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/* DMA_memory_to_memory */ |
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#define DMA_M2M_Enable ((uint32_t)0x00004000) |
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#define DMA_M2M_Disable ((uint32_t)0x00000000) |
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/* DMA_interrupts_definition */ |
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#define DMA_IT_TC ((uint32_t)0x00000002) |
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#define DMA_IT_HT ((uint32_t)0x00000004) |
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#define DMA_IT_TE ((uint32_t)0x00000008) |
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#define DMA1_IT_GL1 ((uint32_t)0x00000001) |
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#define DMA1_IT_TC1 ((uint32_t)0x00000002) |
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#define DMA1_IT_HT1 ((uint32_t)0x00000004) |
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#define DMA1_IT_TE1 ((uint32_t)0x00000008) |
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#define DMA1_IT_GL2 ((uint32_t)0x00000010) |
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#define DMA1_IT_TC2 ((uint32_t)0x00000020) |
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#define DMA1_IT_HT2 ((uint32_t)0x00000040) |
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#define DMA1_IT_TE2 ((uint32_t)0x00000080) |
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#define DMA1_IT_GL3 ((uint32_t)0x00000100) |
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#define DMA1_IT_TC3 ((uint32_t)0x00000200) |
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#define DMA1_IT_HT3 ((uint32_t)0x00000400) |
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#define DMA1_IT_TE3 ((uint32_t)0x00000800) |
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#define DMA1_IT_GL4 ((uint32_t)0x00001000) |
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#define DMA1_IT_TC4 ((uint32_t)0x00002000) |
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#define DMA1_IT_HT4 ((uint32_t)0x00004000) |
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#define DMA1_IT_TE4 ((uint32_t)0x00008000) |
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#define DMA1_IT_GL5 ((uint32_t)0x00010000) |
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#define DMA1_IT_TC5 ((uint32_t)0x00020000) |
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#define DMA1_IT_HT5 ((uint32_t)0x00040000) |
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#define DMA1_IT_TE5 ((uint32_t)0x00080000) |
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#define DMA1_IT_GL6 ((uint32_t)0x00100000) |
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#define DMA1_IT_TC6 ((uint32_t)0x00200000) |
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#define DMA1_IT_HT6 ((uint32_t)0x00400000) |
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#define DMA1_IT_TE6 ((uint32_t)0x00800000) |
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#define DMA1_IT_GL7 ((uint32_t)0x01000000) |
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#define DMA1_IT_TC7 ((uint32_t)0x02000000) |
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#define DMA1_IT_HT7 ((uint32_t)0x04000000) |
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#define DMA1_IT_TE7 ((uint32_t)0x08000000) |
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/* DMA_flags_definition */ |
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#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) |
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#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) |
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#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) |
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#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) |
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#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) |
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#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) |
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#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) |
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#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) |
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#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) |
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#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) |
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#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) |
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#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) |
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#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) |
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#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) |
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#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) |
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#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) |
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#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) |
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#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) |
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#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) |
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#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) |
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#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) |
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#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) |
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#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) |
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#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) |
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#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) |
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#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) |
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#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) |
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#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) |
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void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); |
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void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); |
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void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); |
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void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); |
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void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); |
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void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); |
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uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); |
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FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); |
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void DMA_ClearFlag(uint32_t DMAy_FLAG); |
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ITStatus DMA_GetITStatus(uint32_t DMAy_IT); |
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void DMA_ClearITPendingBit(uint32_t DMAy_IT); |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /*__CH32V00x_DMA_H */
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