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443 lines
12 KiB
443 lines
12 KiB
/********************************** (C) COPYRIGHT ******************************* |
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* File Name : system_ch32v00x.c |
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* Author : WCH |
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* Version : V1.0.0 |
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* Date : 2022/08/08 |
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* Description : CH32V00x Device Peripheral Access Layer System Source File. |
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********************************************************************************* |
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. |
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* Attention: This software (modified or not) and binary are used for |
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* microcontroller manufactured by Nanjing Qinheng Microelectronics. |
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*******************************************************************************/ |
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#include <ch32v00x.h> |
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/* |
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* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after |
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* reset the HSI is used as SYSCLK source). |
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* If none of the define below is enabled, the HSI is used as System clock source. |
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*/ |
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//#define SYSCLK_FREQ_8MHz_HSI 8000000 |
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//#define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE |
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//#define SYSCLK_FREQ_48MHZ_HSI 48000000 |
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//#define SYSCLK_FREQ_8MHz_HSE 8000000 |
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//#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE |
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#define SYSCLK_FREQ_48MHz_HSE 48000000 |
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/* Clock Definitions */ |
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#ifdef SYSCLK_FREQ_8MHz_HSI |
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uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ |
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#elif defined SYSCLK_FREQ_24MHZ_HSI |
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uint32_t SystemCoreClock = SYSCLK_FREQ_24MHZ_HSI; /* System Clock Frequency (Core Clock) */ |
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#elif defined SYSCLK_FREQ_48MHZ_HSI |
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHZ_HSI; /* System Clock Frequency (Core Clock) */ |
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#elif defined SYSCLK_FREQ_8MHz_HSE |
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uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSE; /* System Clock Frequency (Core Clock) */ |
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#elif defined SYSCLK_FREQ_24MHz_HSE |
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uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSE; /* System Clock Frequency (Core Clock) */ |
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#elif defined SYSCLK_FREQ_48MHz_HSE |
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ |
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#else |
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uint32_t SystemCoreClock = HSI_VALUE; |
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#endif |
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__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; |
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/* system_private_function_proto_types */ |
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static void SetSysClock(void); |
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#ifdef SYSCLK_FREQ_8MHz_HSI |
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static void SetSysClockTo_8MHz_HSI(void); |
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#elif defined SYSCLK_FREQ_24MHZ_HSI |
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static void SetSysClockTo_24MHZ_HSI(void); |
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#elif defined SYSCLK_FREQ_48MHZ_HSI |
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static void SetSysClockTo_48MHZ_HSI(void); |
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#elif defined SYSCLK_FREQ_8MHz_HSE |
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static void SetSysClockTo_8MHz_HSE(void); |
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#elif defined SYSCLK_FREQ_24MHz_HSE |
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static void SetSysClockTo_24MHz_HSE(void); |
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#elif defined SYSCLK_FREQ_48MHz_HSE |
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static void SetSysClockTo_48MHz_HSE(void); |
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#endif |
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/********************************************************************* |
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* @fn SystemInit |
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* |
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* @brief Setup the microcontroller system Initialize the Embedded Flash Interface, |
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* the PLL and update the SystemCoreClock variable. |
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* |
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* @return none |
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*/ |
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void SystemInit (void) |
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{ |
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RCC->CTLR |= (uint32_t)0x00000001; |
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RCC->CFGR0 &= (uint32_t)0xFCFF0000; |
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RCC->CTLR &= (uint32_t)0xFEF6FFFF; |
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RCC->CTLR &= (uint32_t)0xFFFBFFFF; |
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RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; |
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RCC->INTR = 0x009F0000; |
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SetSysClock(); |
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} |
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/********************************************************************* |
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* @fn SystemCoreClockUpdate |
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* |
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* @brief Update SystemCoreClock variable according to Clock Register Values. |
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* |
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* @return none |
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*/ |
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void SystemCoreClockUpdate (void) |
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{ |
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uint32_t tmp = 0, pllsource = 0; |
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tmp = RCC->CFGR0 & RCC_SWS; |
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switch (tmp) |
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{ |
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case 0x00: |
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SystemCoreClock = HSI_VALUE; |
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break; |
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case 0x04: |
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SystemCoreClock = HSE_VALUE; |
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break; |
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case 0x08: |
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pllsource = RCC->CFGR0 & RCC_PLLSRC; |
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if (pllsource == 0x00) |
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{ |
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SystemCoreClock = HSI_VALUE * 2; |
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} |
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else |
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{ |
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SystemCoreClock = HSE_VALUE * 2; |
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} |
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break; |
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default: |
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SystemCoreClock = HSI_VALUE; |
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break; |
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} |
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tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; |
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if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) |
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{ |
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SystemCoreClock /= tmp; |
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} |
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else |
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{ |
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SystemCoreClock >>= tmp; |
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} |
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} |
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/********************************************************************* |
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* @fn SetSysClock |
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* |
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. |
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* |
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* @return none |
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*/ |
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static void SetSysClock(void) |
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{ |
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#ifdef SYSCLK_FREQ_8MHz_HSI |
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SetSysClockTo_8MHz_HSI(); |
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#elif defined SYSCLK_FREQ_24MHZ_HSI |
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SetSysClockTo_24MHZ_HSI(); |
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#elif defined SYSCLK_FREQ_48MHZ_HSI |
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SetSysClockTo_48MHZ_HSI(); |
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#elif defined SYSCLK_FREQ_8MHz_HSE |
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SetSysClockTo_8MHz_HSE(); |
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#elif defined SYSCLK_FREQ_24MHz_HSE |
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SetSysClockTo_24MHz_HSE(); |
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#elif defined SYSCLK_FREQ_48MHz_HSE |
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SetSysClockTo_48MHz_HSE(); |
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#endif |
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/* If none of the define above is enabled, the HSI is used as System clock. |
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* source (default after reset) |
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*/ |
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} |
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#ifdef SYSCLK_FREQ_8MHz_HSI |
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/********************************************************************* |
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* @fn SetSysClockTo_8MHz_HSI |
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* |
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* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. |
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* |
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* @return none |
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*/ |
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static void SetSysClockTo_8MHz_HSI(void) |
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{ |
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/* Flash 0 wait state */ |
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); |
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; |
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/* HCLK = SYSCLK = APB1 */ |
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; |
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} |
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#elif defined SYSCLK_FREQ_24MHZ_HSI |
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/********************************************************************* |
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* @fn SetSysClockTo_24MHZ_HSI |
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* |
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* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. |
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* |
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* @return none |
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*/ |
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static void SetSysClockTo_24MHZ_HSI(void) |
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{ |
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/* Flash 0 wait state */ |
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); |
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; |
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/* HCLK = SYSCLK = APB1 */ |
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; |
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} |
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#elif defined SYSCLK_FREQ_48MHZ_HSI |
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/********************************************************************* |
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* @fn SetSysClockTo_48MHZ_HSI |
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* |
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* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. |
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* |
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* @return none |
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*/ |
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static void SetSysClockTo_48MHZ_HSI(void) |
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{ |
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/* Flash 0 wait state */ |
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); |
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; |
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/* HCLK = SYSCLK = APB1 */ |
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; |
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/* PLL configuration: PLLCLK = HSI * 2 = 48 MHz */ |
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); |
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Mul2); |
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/* Enable PLL */ |
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RCC->CTLR |= RCC_PLLON; |
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/* Wait till PLL is ready */ |
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while((RCC->CTLR & RCC_PLLRDY) == 0) |
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{ |
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} |
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/* Select PLL as system clock source */ |
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); |
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; |
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/* Wait till PLL is used as system clock source */ |
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) |
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{ |
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} |
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} |
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#elif defined SYSCLK_FREQ_8MHz_HSE |
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/********************************************************************* |
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* @fn SetSysClockTo_8MHz_HSE |
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* |
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* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. |
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* |
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* @return none |
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*/ |
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static void SetSysClockTo_8MHz_HSE(void) |
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{ |
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
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/* Close PA0-PA1 GPIO function */ |
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RCC->APB2PCENR |= RCC_AFIOEN; |
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AFIO->PCFR1 |= (1<<15); |
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RCC->CTLR |= ((uint32_t)RCC_HSEON); |
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/* Wait till HSE is ready and if Time out is reached exit */ |
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do |
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{ |
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HSEStatus = RCC->CTLR & RCC_HSERDY; |
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StartUpCounter++; |
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
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RCC->APB2PCENR |= RCC_AFIOEN; |
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AFIO->PCFR1 |= (1<<15); |
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if ((RCC->CTLR & RCC_HSERDY) != RESET) |
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{ |
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HSEStatus = (uint32_t)0x01; |
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} |
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else |
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{ |
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HSEStatus = (uint32_t)0x00; |
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} |
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if (HSEStatus == (uint32_t)0x01) |
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{ |
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/* Flash 0 wait state */ |
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); |
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; |
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/* HCLK = SYSCLK = APB1 */ |
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; |
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/* Select HSE as system clock source */ |
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); |
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RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; |
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/* Wait till HSE is used as system clock source */ |
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) |
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{ |
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} |
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} |
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else |
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{ |
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/* |
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* If HSE fails to start-up, the application will have wrong clock |
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* configuration. User can add here some code to deal with this error |
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*/ |
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} |
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} |
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#elif defined SYSCLK_FREQ_24MHz_HSE |
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/********************************************************************* |
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* @fn SetSysClockTo_24MHz_HSE |
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* |
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* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. |
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* |
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* @return none |
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*/ |
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static void SetSysClockTo_24MHz_HSE(void) |
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{ |
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
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/* Close PA0-PA1 GPIO function */ |
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RCC->APB2PCENR |= RCC_AFIOEN; |
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AFIO->PCFR1 |= (1<<15); |
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RCC->CTLR |= ((uint32_t)RCC_HSEON); |
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/* Wait till HSE is ready and if Time out is reached exit */ |
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do |
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{ |
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HSEStatus = RCC->CTLR & RCC_HSERDY; |
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StartUpCounter++; |
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
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RCC->APB2PCENR |= RCC_AFIOEN; |
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AFIO->PCFR1 |= (1<<15); |
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if ((RCC->CTLR & RCC_HSERDY) != RESET) |
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{ |
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HSEStatus = (uint32_t)0x01; |
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} |
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else |
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{ |
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HSEStatus = (uint32_t)0x00; |
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} |
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if (HSEStatus == (uint32_t)0x01) |
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{ |
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/* Flash 0 wait state */ |
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); |
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; |
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/* HCLK = SYSCLK = APB1 */ |
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; |
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/* Select HSE as system clock source */ |
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); |
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RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; |
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/* Wait till HSE is used as system clock source */ |
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) |
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{ |
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} |
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} |
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else |
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{ |
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/* |
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* If HSE fails to start-up, the application will have wrong clock |
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* configuration. User can add here some code to deal with this error |
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*/ |
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} |
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} |
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#elif defined SYSCLK_FREQ_48MHz_HSE |
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/********************************************************************* |
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* @fn SetSysClockTo_48MHz_HSE |
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* |
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* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. |
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* |
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* @return none |
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*/ |
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static void SetSysClockTo_48MHz_HSE(void) |
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{ |
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
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/* Close PA0-PA1 GPIO function */ |
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RCC->APB2PCENR |= RCC_AFIOEN; |
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AFIO->PCFR1 |= (1<<15); |
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RCC->CTLR |= ((uint32_t)RCC_HSEON); |
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/* Wait till HSE is ready and if Time out is reached exit */ |
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do |
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{ |
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HSEStatus = RCC->CTLR & RCC_HSERDY; |
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StartUpCounter++; |
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
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if ((RCC->CTLR & RCC_HSERDY) != RESET) |
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{ |
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HSEStatus = (uint32_t)0x01; |
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} |
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else |
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{ |
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HSEStatus = (uint32_t)0x00; |
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} |
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if (HSEStatus == (uint32_t)0x01) |
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{ |
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/* Flash 0 wait state */ |
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); |
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; |
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/* HCLK = SYSCLK = APB1 */ |
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; |
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/* PLL configuration: PLLCLK = HSE * 2 = 48 MHz */ |
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); |
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE_Mul2); |
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/* Enable PLL */ |
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RCC->CTLR |= RCC_PLLON; |
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/* Wait till PLL is ready */ |
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while((RCC->CTLR & RCC_PLLRDY) == 0) |
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{ |
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} |
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/* Select PLL as system clock source */ |
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); |
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; |
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/* Wait till PLL is used as system clock source */ |
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) |
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{ |
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} |
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} |
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else |
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{ |
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/* |
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* If HSE fails to start-up, the application will have wrong clock |
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* configuration. User can add here some code to deal with this error |
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*/ |
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} |
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} |
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#endif |
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