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164 lines
4.9 KiB
164 lines
4.9 KiB
;/********************************** (C) COPYRIGHT ******************************* |
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;* File Name : startup_ch32v00x.s |
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;* Author : WCH |
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;* Version : V1.0.0 |
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;* Date : 2022/08/08 |
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;* Description : vector table for eclipse toolchain. |
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;********************************************************************************* |
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;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. |
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;* Attention: This software (modified or not) and binary are used for |
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;* microcontroller manufactured by Nanjing Qinheng Microelectronics. |
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;*******************************************************************************/ |
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.section .init, "ax", @progbits |
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.globl _start |
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.align 2 |
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_start: |
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.option norvc; |
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j handle_reset |
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.word 0 |
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.word NMI_Handler /* NMI Handler */ |
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.word HardFault_Handler /* Hard Fault Handler */ |
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.word 0 |
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.word 0 |
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.word 0 |
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.word 0 |
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.word 0 |
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.word 0 |
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.word 0 |
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.word 0 |
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.word SysTick_Handler /* SysTick Handler */ |
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.word 0 |
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.word SW_Handler /* SW Handler */ |
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.word 0 |
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/* External Interrupts */ |
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.word WWDG_IRQHandler /* Window Watchdog */ |
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.word PVD_IRQHandler /* PVD through EXTI Line detect */ |
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.word FLASH_IRQHandler /* Flash */ |
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.word RCC_IRQHandler /* RCC */ |
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.word EXTI7_0_IRQHandler /* EXTI Line 7..0 */ |
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.word AWU_IRQHandler /* AWU */ |
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.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ |
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.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ |
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.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ |
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.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ |
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.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ |
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.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ |
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.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ |
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.word ADC1_IRQHandler /* ADC1 */ |
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.word I2C1_EV_IRQHandler /* I2C1 Event */ |
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.word I2C1_ER_IRQHandler /* I2C1 Error */ |
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.word USART1_IRQHandler /* USART1 */ |
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.word SPI1_IRQHandler /* SPI1 */ |
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.word TIM1_BRK_IRQHandler /* TIM1 Break */ |
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.word TIM1_UP_IRQHandler /* TIM1 Update */ |
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.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ |
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ |
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.word TIM2_IRQHandler /* TIM2 */ |
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.option rvc; |
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.section .text.vector_handler, "ax", @progbits |
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.weak NMI_Handler |
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.weak HardFault_Handler |
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.weak SysTick_Handler |
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.weak SW_Handler |
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.weak WWDG_IRQHandler |
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.weak PVD_IRQHandler |
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.weak FLASH_IRQHandler |
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.weak RCC_IRQHandler |
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.weak EXTI7_0_IRQHandler |
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.weak AWU_IRQHandler |
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.weak DMA1_Channel1_IRQHandler |
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.weak DMA1_Channel2_IRQHandler |
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.weak DMA1_Channel3_IRQHandler |
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.weak DMA1_Channel4_IRQHandler |
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.weak DMA1_Channel5_IRQHandler |
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.weak DMA1_Channel6_IRQHandler |
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.weak DMA1_Channel7_IRQHandler |
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.weak ADC1_IRQHandler |
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.weak I2C1_EV_IRQHandler |
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.weak I2C1_ER_IRQHandler |
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.weak USART1_IRQHandler |
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.weak SPI1_IRQHandler |
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.weak TIM1_BRK_IRQHandler |
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.weak TIM1_UP_IRQHandler |
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.weak TIM1_TRG_COM_IRQHandler |
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.weak TIM1_CC_IRQHandler |
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.weak TIM2_IRQHandler |
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NMI_Handler: 1: j 1b |
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HardFault_Handler: 1: j 1b |
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SysTick_Handler: 1: j 1b |
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SW_Handler: 1: j 1b |
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WWDG_IRQHandler: 1: j 1b |
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PVD_IRQHandler: 1: j 1b |
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FLASH_IRQHandler: 1: j 1b |
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RCC_IRQHandler: 1: j 1b |
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EXTI7_0_IRQHandler: 1: j 1b |
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AWU_IRQHandler: 1: j 1b |
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DMA1_Channel1_IRQHandler: 1: j 1b |
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DMA1_Channel2_IRQHandler: 1: j 1b |
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DMA1_Channel3_IRQHandler: 1: j 1b |
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DMA1_Channel4_IRQHandler: 1: j 1b |
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DMA1_Channel5_IRQHandler: 1: j 1b |
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DMA1_Channel6_IRQHandler: 1: j 1b |
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DMA1_Channel7_IRQHandler: 1: j 1b |
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ADC1_IRQHandler: 1: j 1b |
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I2C1_EV_IRQHandler: 1: j 1b |
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I2C1_ER_IRQHandler: 1: j 1b |
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USART1_IRQHandler: 1: j 1b |
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SPI1_IRQHandler: 1: j 1b |
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TIM1_BRK_IRQHandler: 1: j 1b |
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TIM1_UP_IRQHandler: 1: j 1b |
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TIM1_TRG_COM_IRQHandler: 1: j 1b |
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TIM1_CC_IRQHandler: 1: j 1b |
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TIM2_IRQHandler: 1: j 1b |
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.section .text.handle_reset, "ax", @progbits |
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.weak handle_reset |
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.align 1 |
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handle_reset: |
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.option push |
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.option norelax |
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la gp, __global_pointer$ |
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.option pop |
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1: |
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la sp, _eusrstack |
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2: |
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/* Load data section from flash to RAM */ |
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la a0, _data_lma |
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la a1, _data_vma |
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la a2, _edata |
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bgeu a1, a2, 2f |
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1: |
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lw t0, (a0) |
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sw t0, (a1) |
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addi a0, a0, 4 |
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addi a1, a1, 4 |
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bltu a1, a2, 1b |
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2: |
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/* clear bss section */ |
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la a0, _sbss |
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la a1, _ebss |
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bgeu a0, a1, 2f |
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1: |
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sw zero, (a0) |
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addi a0, a0, 4 |
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bltu a0, a1, 1b |
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2: |
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li t0, 0x80 |
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csrw mstatus, t0 |
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li t0, 0x3 |
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csrw 0x804, t0 |
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la t0, _start |
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ori t0, t0, 3 |
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csrw mtvec, t0 |
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jal SystemInit |
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la t0, main |
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csrw mepc, t0 |
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mret |
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